module Register (
	input clk,
	input rst_n,
	input D,
	output Q
);
	wire nand1, nand2, nand3, nand4;
	wire mux_out;

	nand(nand1, D, clk);
	nand(nand3, nand1, clk);
	nand(nand4, nand2, nand3);
	nand(nand2, nand1, nand4);

	Mux2To1 mux (
		.sel(~rst_n),
		.a(nand2),
		.b(1'b0),
		.out(mux_out)
	);

	assign Q = mux_out;
endmodule


module MyDFF(
	input rst_n,
	input clk,
	input D,
	output Q_out
);
	wire Q1, Q2;
	wire nclk;
	not(nclk, clk);
	
	Register reg1 (
		.clk(nclk),
		.rst_n(rst_n),
		.D(D),
		.Q(Q1)
	);
	Register reg2 (
		.clk(clk),
		.rst_n(rst_n),
		.D(Q1),
		.Q(Q2)
	);
	wire mux_out;

	Mux2To1 mux_rst (
		.sel(~rst_n),
		.a(Q2),
		.b(1'b0),
		.out(mux_out)
	);

	assign Q_out = mux_out;

endmodule
